First 3D processor runs at 1.4 Ghz

 

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Posted on 22 Sep 2008 at 12:41

Engineers have made a key breakthrough in the race to make next-generation three-dimensional computer processors with the development of functional three-dimensional synchronisation circuitry.

The so-called 'Rochester Cube', which was developed at the US University of Rochester, is now running at 1.4Ghz. Unlike past attempts at creating 3D chips, the Cube is not made of several standard processors stacked on top of each another. Instead it was designed and built to optimise all key processing functions vertically, through multiple layers of processors, the same way ordinary chips optimise functions horizontally.

According to its creators, this design means tasks such as synchronicity, power distribution and long-distance signalling are all fully functioning in three dimensions for the first time.

"I call it a cube now, because it's not just a chip anymore," said Eby Friedman, professor of electrical and computer engineering at Rochester.

"This is the way computing is going to have to be done in the future.
When the chips are flush against each other, they can do things you could never do with a regular 2D chip," he added.

Friedman, working with engineering student Vasilis Pavlidis, argues that adoption of three-dimensional architectures is essential if processor capacities are to continue increasing at current rates. This is because developers are approaching the point when it will become impossible to pack more chips next to each other on circuit boards, and so must begin stacking them on top of each other.

"Are we going to hit a point where we can't scale integrated circuits any smaller? Horizontally, yes," said Friedman. "But we're going to start scaling vertically, and that will never end. At least not in my lifetime; talk to my grandchildren about that."

However, Friedman does acknowledge that vertical expansion will create "a host of difficulties". He said the key is to design a 3D chip where all the layers interact like a single system.

According to the researchers, getting all three levels of the 3D chip to act in harmony is like trying to devise a traffic control system for the entire United States - and then layering two more United States above the first. Somehow developers must devise a way of getting every bit of traffic from any point on any level to its destination on any other level, while simultaneously coordinating the traffic of millions of other drivers.

Complicate that by changing the two United States layers to something like China and India where the driving laws and roads are quite different, and the complexity and challenge of designing a single control system to work in any chip begins to become apparent, according to Friedman.

To combat these issues the professor and his students' design allows for different impedances that might occur from chip to chip, different operating speeds, and different power requirements.

Author: Robert Jaques